--TD 4.1.1 Source Connect Sink Test
baselib.report(0x00, "TD4.2.1 beginning.")   
--第一步:如果VIF字段Captive_Cable设置为YES,CVS模拟一个插座连接器;否则,CVS模拟一个主动电缆
--原文:If VIF field Captive_Cable is set to YES, CVS emulates a receptacle as per condition 1 in Section D above, otherwise CVS emulates an Active cable as per condition 2

--第二步:CVS验证PUT在测试的剩余部分不应用Rd(注意:这是为了检查连接时的Rd/Rp切换)
--原文:CVS verifies PUT does not apply Rd for the remainder of the test (Note: This is to check for toggling between Rd/Rp for connect)
local monitor1 = busilib.newMonitor(TMD.CHECK_POINT, 0, {2}, {0}, {0})           --监测CC1是否有超过1600mV,没有提供Rd的话电压会比较高
local monitor2 = busilib.newMonitor(TMD.CHECK_POINT, 1, {2}, {0}, {0})           --监测CC2是否有超过1600mV
--第三步:如果VIF字段Type_C_Sources_Vconn为NO,CVS验证PUT在测试的剩余部分不提供Vconn
--原文:If VIF field Type_C_Sources_Vconn is NO, CVS verifies PUT does not source Vconn for the remainder of this test.

--接第二步:测试剩余部分
if busilib.getMonitorResult(monitor1) == 1 and busilib.getMonitorResult(monitor2) == 1 then     --结果都是1说明CC电压都超过1600mV,PUT没有提供Rd
    baselib.report(0x00, "TD.4.2.1.V.1 pass.") 
else
    baselib.report(0x00, "TD.4.2.1.V.1 fail.") 